In recent years, with the advances in digital technologies employed for electronic apparatuses, large-capacity and non-volatile semiconductor memory devices for storing data, such as music, images, and information, have been actively developed. For example, a non-volatile semiconductor memory device using a ferroelectric as a capacitive element has already been used in many fields. In comparison with such a non-volatile semiconductor memory device using a ferroelectric capacitor, there is a non-volatile semiconductor memory device using a material that changes in resistance in response to the application of an electrical pulse and keeps the resulting state (referred to as the ReRAM hereafter). This ReRAM has received attention because consistency with a usual semiconductor process can be easily ensured (see Patent Literatures 1 and 2, for example).
With the aim of reducing the size and increasing the capacity for a memory element, a cross point ReRAM has been proposed. In the cross point ReRAM, a memory cell is formed at an intersection of an upper line and a lower line. This memory cell has a structure where a variable resistance layer is positioned between an upper electrode and a lower electrode. Moreover, each memory cell includes a diode inserted in series with the variable resistance layer. With this, when a resistance value of the variable resistance layer included in the memory cell is read, this memory cell can avoid influence (such as a leakage current) of another memory cell on a different row or column in a two-dimensional memory cell array.
FIG. 19 is a cross-section diagram showing, as a first example of the aforementioned cross point ReRAM, a non-volatile semiconductor memory device 1000 including a conventional variable resistance element (see Patent Literature 1). More specifically, FIG. 19 is a cross-section diagram of a memory cell 1280 along a bit-line direction, a bit line 1210, and a word line 1220. A variable resistance element 1260 includes: a variable resistance layer 1230 storing information according to an electrical-resistance change in response to an electrical stress; an upper electrode 1240; and a lower electrode 1250. Here, the variable resistance layer 1230 is positioned between the upper electrode 1240 and the lower electrode 1250. A two-terminal nonlinear element 1270 having nonlinear current-voltage characteristics capable of passing current bidirectionally is formed on the variable resistance element 1260. Thus, a series circuit of the variable resistance element 1260 and the nonlinear element 1270 form the memory cell 1280. The nonlinear element 1270 is a two-terminal element, such as a diode, that has the nonlinear current-voltage characteristics whereby a current change is not consistent with a voltage change. Moreover, the bit line 1210 which is the upper line is electrically connected to the nonlinear element 1270, and the word line 1220 which is the lower line is electrically connected to the lower electrode 1250 of the variable resistance element 1260.
As a second example, Patent Literature 2 discloses a specific configuration and manufacturing method of a non-volatile semiconductor memory element into which a diode is inserted in series. The non-volatile semiconductor memory element disclosed in Patent Literature 2 includes: an electrode layer having a diode which is a non-ohmic characteristic element; at least one of an insulator layer or a semiconductor layer; and an interlayer insulating layer. Here, the electrode layer and the insulator or semiconductor layer are filled in a memory cell hole formed in the interlayer insulating layer. With this configuration, a front surface of the non-ohmic element can be formed smooth and flush with the interlayer insulating layer, and thus a favorable interfacial state of the non-ohmic element can be obtained. As a result, a decrease or variations in resistance to pressure due to, for example, electric field concentration can be prevented, and a current capacity can be increased.